Vhdl Fixed Point Synthesis Essay

 

That is correct.

 

 

A floating point datapath is like any other logic circuit which must be instantiated.  If you design the datapath to handle mult, add, and sub -- that is what you should expect.  Or you can add an embedded processor and implement FP arithmetic in software/firmware routines.  Xilinx and Xilinx partners offer FP IP cores.  I'm sure there are freeware FP math cores to be found at opencores.org.

 

 

FP math is generally quite complex compared to integer math.  If your needs are complex, the implementation (and debugging and verification) can take months.  It is easy to get bogged down in the details of the corner cases -- the unusual combinations of operands which produce unusual results -- and the various possible implementations of rounding modes.

 

You have made a common mistake.  There is an abundance of information in these forums and on the web about FP arithmetic and hardware implementations.

 

If you can avoid using FP arithmetic -- using integer or fixed point arithmetic instead (also called "block floating point") -- you will likely save yourself much time and a considerable amount of FPGA resources.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

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